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| ?2002 integrated device technology, inc. dsc-5624/3 1 preliminary IDT70V35/34s/l high-speed 3.3v 8/4k x 18 dual-port static ram IDT70V35/34 easily expands data bus width to 36 bits or more using the master/slave select when cascading more than one device m/ s = v ih for busy output flag on master m/ s = v il for busy input on slave busy and interrupt flag on-chip port arbitration logic full on-chip hardware support of semaphore signaling between ports fully asynchronous operation from either port lvttl-compatible, single 3.3v (0.3v) power supply available in a 100-pin tqfp industrial temperature range (-40c to +85c) is available for selected speeds notes: 1. a 12 is a nc for idt70v34. 2. (master): busy is output; (slave): busy is input. 3. busy outputs and int outputs are non-tri-stated push-pull. true dual-ported memory cells which allow simultaneous reads of the same memory location high-speed access ? commercial: 15/20/25ns (max.) ? industrial: 20ns low-power operation ? IDT70V35/34s active: 430mw (typ.) standby: 3.3mw (typ.) ? IDT70V35/34l active: 415mw (typ.) standby: 660 w (typ.) separate upper-byte and lower-byte control for multiplexed bus compatibility i/o control address decoder memory array arbitration interrupt semaphore logic address decoder i/o control r/ w l busy l a 12l (1) a 0l 5624 drw 01 ub l lb l ce l oe l i/o 9l -i/o 17l i/o 0l -i/o 8l ce l oe l r/ w l sem l int l m/ s r/ w r busy r ub r lb r ce r oe r i/o 9r -i/o 17r i/o 0r -i/o 8r a 12r (1) a 0r r/ w r sem r int r ce r oe r (3) (2,3) (2,3) (3) 13 13 , 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 2 the IDT70V35/34 is a high-speed 8/4k x 18 dual-port static ram. the IDT70V35/34 is designed to be used as a stand-alone dual-port ram or as a combination master/slave dual-port ram for 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. this device provides two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature controlled by ce permits the on-chip circuitry of each port to enter a very low standby power mode. fabricated using idt?s cmos high-performance technology, these devices typically operate on only 430mw of power. the IDT70V35/34 is packaged in a plastic 100-pin thin quad flatpack. !" notes: 1. a 12 is a nc for idt70v34. 2. all v cc pins must be connected to power supply. 3. all gnd pins must be connected to ground. 4. pn100-1 package body is approximately 14mm x 14mm x 1.4mm. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part marking. index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 IDT70V35/34pf pn100-1 (5) 100-pin tqfp top view (6) n/c n/c i/o 8l i/o 17l i/o 11l i/o 12l i/o 13l i/o 14l gnd i/o 15l i/o 16l v cc gnd i/o 0r i/o 1r i/o 2r i/o 3r v cc i/o 4r i/o 5r i/o 6r i/o 8r i/o 17r n/c n/c 5624 drw 02 n/c n/c n/c n/c a 5l a 4l a 3l a 2l a 1l a 0l int l gnd m/ s busy r int r a 0r n/c n/c n/c n/c busy l a 1r a 2r a 3r a 4r i / o 1 0 l i / o 9 l i / o 7 l i / o 6 l i / o 5 l i / o 4 l i / o 3 l i / o 2 l g n d i / o 1 l i / o 0 l o e l v c c r / w l s e m l c e l u b l l b l a 1 1 l a 1 0 l a 9 l a 8 l a 7 l a 6 l i / o 7 r i / o 9 r i / o 1 0 r i / o 1 1 r i / o 1 2 r i / o 1 3 r i / o 1 4 r i / o 1 5 r g n d i / o 1 6 r o e r r / w r s e m r c e r u b r l b r g n d a 1 1 r a 1 0 r a 9 r a 8 r a 7 r a 6 r a 5 r a 1 2 l ( 1 ) a 1 2 r ( 1 ) , 07/02/02 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 3 # $#%&'( ) *+,- # $#%&&'.$*+,- " note: 1. a 0l ? a 12l a 0r ? a 12r note: 1. there are eight semaphore flags written to via i/o 0 and read from all of the i/o's (i/o 0 -i/o 17 ). these eight semaphores are addressed by a 0 -a 2 . inputs (1 ) outputs mode ce r/ w oe ub lb sem i/o 9-17 i/o 0-8 h x x x x h high-z high-z deselected: power down x x x h h h high-z high-z both bytes deselected llxlhhdata in high-z write to upper byte only l l x h l h high-z data in write to lowe r byte only llxllhdata in data in write to bo th byte s lhllhhdata out high-z read upper byte only lhlhlhhigh-zdata out read lower byte only lhlllhdata out data out read both bytes x x h x x x high-z high-z outputs disabled 56 24 tbl 02 inputs outputs mode ce r/ w oe ub lb sem i/o 9-17 i/o 0-8 hhlxxldata out data out read data in semaphore flag xhlhhldata out data out read data in semaphore flag h xxxldata in data in write i/o 0 into semaphore flag x xhhldata in data in write i/o 0 into semaphore flag lxxlxl ____ ____ not allowed lxxxll ____ ____ not allowed 56 24 tb l 03 ( left port right port names ce l ce r chip enable r/ w l r/ w r read/write enable oe l oe r output enable a 0l - a 12l (1 ) a 0r - a 12r (1 ) address i/o 0l - i/o 17l i/o 0r - i/o 17r data input/output sem l sem r semaphore enable ub l ub r upp er byte se lect lb l lb r lower byte select int l int r interrup t flag busy l busy r busy flag m/ s master or slave select v cc power (3.3v) gnd ground (0v) 5624 tbl 01 1. a 12 is a nc for idt70v34. 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 4 /% 01 * " 01 2 # +. 34 " " # / 5678 5 90:;" * ++2 + notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed vcc + 0.3v. notes: 1. this parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0v to 3v or from 3v to 0v. note: 1. this is the parameter t a . this is the "instant on" case temperature. notes: 1. v il > -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 0.3v. < $ 2= $2 # +. 34 * 4 5 9 4>9 4" note: 1. at vcc < 2.0v leakages are undefined. symbol rating commercial & industrial unit v te rm (2 ) terminal voltage with respect to gnd -0.5 to +4.6 v t bias te m p e ra tu r e under bias -55 to +125 o c t stg storage te m p e ra tu r e -65 to +150 o c i out dc output current 50 ma 5624 tbl 04 grade ambient temperature gnd vcc commercial 0 o c to +70 o c0v 3.3v + 0.3v industrial -40 o c to +85 o c0v 3.3v + 0.3v 5624 tbl 05 symbol parameter min. typ. max. unit v cc supply voltage 3.0 3.3 3.6 v gnd ground 0 0 0 v v ih input high voltage 2.0 ____ v cc +0.3 (2 ) v v il input low voltage -0.3 (1 ) ____ 0.8 v 5624 tbl 06 symbol parameter conditions (2 ) max. unit c in input capacitance v in = 3dv 9 pf c out output capacitance v out = 3dv 10 pf 5624 tbl 07 symbol parameter test conditions 70v35/34s 70v35/34l unit min. max. min. max. |i li | input leakage current (1 ) v cc = 3.6v, v in = 0v to v cc ___ 10 ___ 5a |i lo | output leakage currentt (1 ) ce = v ih , v out = 0v to v cc ___ 10 ___ 5a v ol output low voltage i ol = +4ma ___ 0.4 ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 5624 tbl 08 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 5 < $ 2= $2 # +. 34 * " 4 5 9 4>9 4" notes: 1. 'x' in part number indicates power rating (s or l) 2. v cc = 3.3v, t a = +25 c, and are not production tested. icc dc = 115ma (typ.) 3. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/t rc , and using ? ac test conditions ? of input levels of gnd to 3v. 4. f = 0 means no address or control lines change. 5. port "a" may be either left or right port. port "b" is the opposite from port "a". 70v35/34x15 com'l only 70v35/34x20 com'l & ind 70v35/34x25 com'l only symbol parameter test condition version typ. (2 ) max. typ. (2 ) max. typ. (2 ) max. unit i cc dynamic ope rating curre nt (both ports active) ce = v il , outputs disabled sem = v ih f = f max (3 ) com'l s l 150 140 215 185 140 130 200 175 130 125 190 165 ma ind s l ____ ____ ____ ____ 140 130 225 195 ____ ____ ____ ____ i sb1 standby current (both ports - ttl level inputs) ce r and ce l = v ih sem r = sem l = v ih f = f max (3 ) com'l s l 25 20 35 30 20 15 30 25 16 13 30 25 ma mil & ind s l ____ ____ ____ ____ 20 15 45 40 ____ ____ ____ ____ i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5 ) active port outputs disabled, f=f max (3 ) sem r = sem l = v ih com'l s l 85 80 120 110 80 75 110 100 75 72 110 95 ma mil & ind s l ____ ____ ____ ____ 80 75 130 115 ____ ____ ____ ____ i sb3 full standby current (both ports - cmos level inp uts) both ports ce l and ce r > v cc - 0.2v, v in > v cc - 0.2v or v in < 0.2v, f = 0 (4 ) sem r = sem l > v cc -0.2v com'l s l 1.0 0.2 5 2.5 1.0 0.2 5 2.5 1.0 0.2 5 2.5 ma mil & ind s l ____ ____ ____ ____ 1.0 0.2 15 5 ____ ____ ____ ____ i sb4 full standby current (one port - cmos level inp uts) ce "a" < 0.2v and ce "b" > v cc - 0.2v (5 ) sem r = sem l > v cc -0.2v v in > v cc - 0.2v or v in < 0.2v active port outputs disabled, f = f max (3 ) com'l s l 85 80 125 105 80 75 115 100 75 70 105 90 ma mil & ind s l ____ ____ ____ ____ 80 75 130 115 ____ ____ ____ ____ 5624 tbl 09 /# + figure 1. ac output test load input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 3ns max. 1.5v 1.5v figures 1 and 2 5624 tbl 10 figure 2. output test load (for t lz , t hz , t wz , t ow ) *including scope and jig. 5624 drw 03 590 ? 30pf 435 ? 3.3v data out busy int 590 ? 5pf* 435 ? 3.3v data out , # ?)?)? ce 5624 drw 04 t pu i cc i sb t pd 50% 50% , 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 6 -= *+3 7" notes: 1. timing depends on which signal is asserted last, oe , ce , lb , or ub . 2. timing depends on which signal is de-asserted first, ce , oe , lb , or ub . 3. t bdd delay is required only in case where opposite port is completing a write operation to the same address location for simultaneo us read operations busy has no relation to valid output data. 4. start of valid data depends on which timing becomes effective last t abe , t aoe , t ace , t aa or t bdd . 5. sem = v ih . t rc r/ w ce addr t aa oe ub , lb 5624 drw 05 (4) t ace (4) t aoe (4) t abe (4) (1) t lz t oh (2) t hz (3,4) t bdd data out busy out valid data (4) /< $ 2= $ 2 # +. 34 * !" notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram, ce = v il , ub or lb = v il , and sem = v ih . to access semaphore, ce = v ih or ub & lb = v ih , and sem = v il . 4. 'x' in part number indicates power rating (s or l). 70v35/34x15 com'l only 70v35/34x20 com'l & ind 70v35/34x25 com'l only unit symbol parameter min.max.min.max.min.max. read cycle t rc read cycle time 15 ____ 20 ____ 25 ____ ns t aa address access time ____ 15 ____ 20 ____ 25 ns t ace chip enable access time (3 ) ____ 15 ____ 20 ____ 25 ns t abe byte enable access time (3 ) ____ 15 ____ 20 ____ 25 ns t aoe output enable access time (3 ) ____ 10 ____ 12 ____ 13 ns t oh output hold from address change 3 ____ 3 ____ 3 ____ ns t lz output low-z time (1,2) 3 ____ 3 ____ 3 ____ ns t hz output high-z time (1,2) ____ 10 ____ 12 ____ 15 ns t pu chip enable to power up time (1,2) 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (1,2) ____ 15 ____ 20 ____ 25 ns t sop semaphore flag update pulse ( oe or sem )10 ____ 10 ____ 10 ____ ns t saa semaphore address access (3 ) ____ 15 ____ 20 ____ 25 ns 5624 tbl 11 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 7 /< $ 2= $ 2 # +. 34 7" notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access sram, ce = v il , ub or lb = v il , sem = v ih . to access semaphore, ce = v ih or ub & lb = v ih , and sem = v il . either condition must be valid for the entire t ew time. 4. the specification for t dh must be met by the device supplying write data to the sram under all operating conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . 5. 'x' in part number indicates power rating (s or l). symbol parameter 70v35/34x15 com'l only 70v35/34x20 com'l & ind 70v35/34x25 com'l only unit min. max. min. max. min. max. write cycle t wc write cycle time 15 ____ 20 ____ 25 ____ ns t ew chip enable to end-of-write (3) 12 ____ 15 ____ 20 ____ ns t aw address valid to end-of-write 12 ____ 15 ____ 20 ____ ns t as address set-up time (3) 0 ____ 0 ____ 0 ____ ns t wp write pulse width 12 ____ 15 ____ 20 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 10 ____ 15 ____ 15 ____ ns t hz output high-z time (1,2) ____ 10 ____ 12 ____ 15 ns t dh data ho ld time (4) 0 ____ 0 ____ 0 ____ ns t wz write enable to output in high-z (1,2) ____ 10 ____ 12 ____ 15 ns t ow output active from end-of-write (1, 2,4 ) 0 ____ 0 ____ 0 ____ ns t swrd sem flag write to read time 5 ____ 5 ____ 5 ____ ns t sps sem flag contention window 5 ____ 5 ____ 5 ____ ns 5624 tbl 12 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 8 # -= - 3 (9 *, w +# 7 @" notes: 1. r/ w or ce or ub & lb must be high during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a low ub or lb and a low ce and a low r/ w for memory array writing cycle. 3. t wr is measured from the earlier of ce or r/ w (or sem or r/ w ) going high to the end-of-write cycle. 4. during this period, the i/o pins are in the output state and input signals must not be applied. 5. if the ce or sem low transition occurs simultaneously with or after the r/ w low transition the outputs remain in the high-impedance state. 6. timing depends on which enable signal is asserted last, ce , r/ w , or ub or lb . 7. this parameter is guaranteed by device characterization, but is not production tested. transition is measured 0mv from steady state with output test load (figure 2). 8. if oe is low during r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during an r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 9. to access sram, ce = v il , ub or lb = v il , and sem = v ih . to access semaphore, ce = v ih or ub and lb = v ih , and sem = v il . t ew must be met for either condition. # -= - 3 (9 ce ub lb +# 7" r/ w t wc t hz t aw t wr t as t wp data out (2) t wz t dw t dh t ow oe address data in (6) (4) (4) (7) ce or sem 5624 drw 08 (9) ce or sem (9) (7) (3) 5624 drw 07 t wc t as t wr t dw t dh address data in r/ w t aw t ew ub or lb (3) (2) (6) ce or sem (9) (9) 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 9 # -= .$*+ - # < $. + " # -= .$- !" notes: 1. d or = d ol = v il , ce r = ce l = v ih , or both ub & lb = v ih . 2. all timing is the same for left and right port. port ? a ? may be either left or right port. port ? b ? is the opposite from port ? a ? . 3. this parameter is measured from r/ w "a" or sem "a" going high to r/ w "b" or sem "b" going high. 4. if t sps is not satisfied, there is no guarantee which side will obtain the semaphore flag. notes: 1. ce = v ih or ub & lb = v ih for the duration of the above timing (both write and read cycle). 2. ? data out valid ? represents all i/o's (i/o 0 -i/o 17 ) equal to the semaphore value. sem 5624 drw 08 t aw t ew t sop i/o 0 valid address t saa r/ w t wr t oh t ace valid address data in valid data out t dw t wp t dh t as t swrd t aoe read cycle write cycle a 0 -a 2 oe valid (2) sem "a" 5624 drw 09 t sps match r/ w "a" match a 0"a" -a 2"a" side "a" (2) sem "b" r/ w "b" a 0"b" -a 2"b" side (2) "b" 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 10 5624 drw 10 t aps addr "a" t wc data out "b" match t wp r/ w "a" data in "a" addr "b" t dh valid (1) match busy "b" t bda valid t bdd t ddd (3) t wdd t baa t dw # -= - ) ) *+ + busy ! 7" 0, s 54 &: " notes: 1. to ensure that the earlier of the two ports wins. t aps is ignored for m/ s = v il (slave). 2. ce l = ce r = v il. 3. oe = v il for the reading port. 4. if m/ s = v il (slave), busy is an input. then for this example busy ? a ? = v ih and busy ? b ? input is shown above. 5. all timing is the same for both left and right ports. port ? a ? may be either the left or right port. port ? b ? is the port opposite from port ? a ? . /< $ 2= $ 2 # +. 34 * a" notes: 1. port-to-port delay through sram cells from writing port to reading port, refer to "timing waveform of write port-to-port read and busy (m/ s = v ih )". 2. to ensure that the earlier of the two ports wins. 3. t bdd is a calculated parameter and is the greater of 0, t wdd ? t wp (actual) or t ddd ? t dw (actual). 4. to ensure that the write cycle is inhibited during contention. 5. to ensure that a write cycle is completed after contention. 6. 'x' in part number indicates power rating (s or l). 70v35/34x15 com'l ony 70v35/34x20 com'l & ind 70v35/34x25 com'l only symbol parameter min. max. min. max. min. max. unit busy timing (m/ s = v ih ) t baa busy access time from address match ____ 15 ____ 20 ____ 20 ns t bda busy disabl e time fro m ad dress no t matche d ____ 15 ____ 20 ____ 20 ns t bac busy access time from chip enable low ____ 15 ____ 20 ____ 20 ns t bdc busy disable time from chip enable high ____ 15 ____ 17 ____ 17 ns t aps arb itration priority se t-up time (2) 5 ____ 5 ____ 5 ____ ns t bdd busy disable to valid data (3) ____ 18 ____ 30 ____ 30 ns t wh write hold after busy (5) 12 ____ 15 ____ 17 ____ ns busy timing (m/ s = v il ) t wb busy inp ut to write (4) 0 ____ 0 ____ 0 ____ ns t wh write hold after busy (5) 12 ____ 15 ____ 17 ____ ns port-to-port delay timing t wdd write pulse to data delay (1) ____ 30 ____ 45 ____ 50 ns t ddd write data valid to read data delay (1) ____ 25 ____ 35 ____ 35 ns 5624 tbl 1 3 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 11 # -= - ? $ busy -= busy /% +%3 ce # " 0, s 54 &: " -= busy /% 3 +%3/++0 $ # " 0, s 54 &: " notes: 1. all timing is the same for left and right ports. port ? a ? may be either the left or right port. port ? b ? is the port opposite from ? a ? . 2. if t aps is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. 5624 drw 11 r/ w "a" busy "b" t wp t wb r/ w "b" t wh (2) (3) (1) , notes: 1. t wh must be met for both master busy input (slave) and output (master). 2. busy is asserted on port "b" blocking r/ w "b" , until busy "b" goes high. 3. t wb is only for the slave version. 5624 drw 12 addr "a" and "b" addresses match ce "a" ce "b" busy "b" t aps t bac t bdc (2) 5624 drw 13 addr "a" address "n" addr "b" busy "b" t aps t baa t bda (2) matching address "n" 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 12 -= & # " notes: 1. all timing is the same for left and right ports. port ? a ? may be either the left or right port. port ? b ? is the port opposite from ? a ? . 2. see interrupt flag truth table iii. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first. 5624 drw 14 addr "a" interrupt set address ce "a" r/ w "a" t as t wc t wr (3) (4) t ins (3) int "b" (2) 5624 drw 15 addr "b" interrupt clear address ce "b" oe "b" t as t rc (3) t inr (3) i nt "b" (2) /< $ 2= $ 2 # +. 34 * " notes: 1. 'x' in part number indicates power rating (s or l). 70v35/34x15 com'l only 70v35/34x20 com'l & ind 70v35/34x25 com'l only symbol parameter min.max.min.max.min.max.unit interrupt timing t as address set-up time 0 ____ 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t ins interrupt set time ____ 15 ____ 20 ____ 20 ns t inr interrupt reset time ____ 15 ____ 20 ____ 20 ns 5624 tbl 14 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 13 # $#%&&&b& " notes: 1. assumes busy l = busy r = v ih . 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. 4. a 12 is a nc for idt70v34, therefore interrupt addresses are fff and ffe. left port right port function r/ w l ce l oe l a 12l -a 0l (4) int l r/ w r ce r oe r a 12r -a 0r (4) int r llx1fff (4) xxxx x l (2) set rig ht int r flag xxxxxxll1fff (4) h (3) reset right int r flag xxx x l (3) llx1ffe (4) xset left int l flag xll1ffe (4) h (2) x x x x x re se t left int l flag 56 24 tb l 15 # $#%4b<1 .$ .c " notes: 1. this table denotes a sequence of events for only one of the eight semaphores on the IDT70V35/34. 2. there are eight semaphore flags written to via i/o 0 and read from all i/o's (i/o 0 -i/o 17 ). these eight semaphores are addressed by a 0 -a 2 . 3. ce = v ih , sem = v il to access the semaphores. refer to the semaphore read/write control truth tables. functions d 0 - d 17 left d 0 - d 17 right status no action 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token right port writes "0" to semaphore 0 1 no change. right side has no write access to semaphore left port writes "1" to semaphore 1 0 right port obtains semaphore token left port writes "0" to semaphore 1 0 no change. left port has no write access to semaphore right port writes "1" to semaphore 0 1 left port obtains semaphore token left port writes "1" to semaphore 1 1 semaphore free right port writes "0" to semaphore 1 0 right port has semaphore token right port writes "1" to semaphore 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token left port writes "1" to semaphore 1 1 semaphore free 5624 tbl 17 # $#%&4b/++ busy /% notes: 1. pins busy l and busy r are both outputs when the part is configured as a master. both are inputs when configured as a slave. busy outputs on the IDT70V35/ 34 are push pull, not open drain outputs. on slaves the busy input internally inhibits writes. 2. l if the inputs to the opposite port were stable prior to the address and enable inputs of this port. v ih if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = low will result. busy l and busy r outputs cannot be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of actual logic level on the pin. 4. a 12 is a nc for idt70v34. address comparison will be for a 0 - a 11 . inputs outputs function ce l ce r a 12l -a 0l (4 ) a 12r -a 0r busy l (1 ) busy r (1 ) xxno matchhhnormal hxmatchhhnormal xhmatchhhnormal ll match note (2 ) no te (2 ) write inhibit (3 ) 5624 tbl 16 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 14 figure 3. busy and chip enable routing for both width and depth expansion with IDT70V35/34 srams. programmed by tying the busy pins high. if desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. the busy outputs on the idt 70v35/34 sram in master mode, are push-pull type outputs and do not require pull up resistors to operate. if these srams are being expanded in depth, then the busy indication for the resulting array requires the use of an external and gate. - + $<1 ? $ 3 0 ,.=/3 when expanding an IDT70V35/34 sram array in width while using busy logic, one master part is used to decide which side of the sram array will receive a busy indication, and to output that indication. any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. thus on the IDT70V35/34 sram the busy pin is an output if the part is used as a master (m/ s pin = v ih ), and the busy pin is an input if the part used as a slave (m/ s pin = v il ) as shown in figure 3. if two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. this would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. the busy arbitration, on a master, is based on the chip enable and address signals only. it ignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with either the r/ w signal or the byte enables. failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. .$ the IDT70V35/34 is an extremely fast dual-port 8/4k x 18 cmos static ram with an additional 8 address locations dedicated to binary semaphore flags. these flags allow either processor on the left or right side of the dual-port sram to claim a privilege over the other processor for functions defined by the system designer ? s software. as an example, the semaphore can be used by one processor to inhibit the the IDT70V35/34 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the IDT70V35/34 has an automatic power down feature controlled by ce . the ce controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce high). when a port is enabled, access to the entire memory array is permitted. & if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location 1ffe (hex), where a write is defined as the ce r = r/ w r = v il per truth table iii. the left port clears the interrupt by an address location 1ffe access when ce l = oe l = v il , r/ w l is a "don't care". likewise, the right port interrupt flag ( int r ) is set when the left port writes to memory location 1fff (hex) (fff for idt70v34) and to clear the interrupt flag ( int r ), the right port must read the memory location 1fff. the message (16 bits) at 1ffe or 1fff (ffe or fff for idt70v34) is user-defined, since it is an addressable sram location. if the interrupt function is not used, address locations 1ffe and 1fff (ffe and fff for idt70v34) are not used as mail boxes, but as part of the random access memory. refer to truth table iii for the interrupt operation. 3 busy logic provides a hardware indication that both ports of the sram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the sram is ? busy ? . the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applica- tions. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. if the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the m/ s pin. once in slave mode the busy pin operates solely as a write inhibit input pin. normal operation can be 5624 drw 16 master dual port sram busy l busy r ce master dual port sram busy l busy r ce slave dual port sram busy l busy r ce slave dual port sram busy l busy r ce busy l busy r d e c o d e r 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 15 other from accessing a portion of the dual-port sram or any other shared resource. the dual-port sram features a fast access time, and both ports are completely independent of each other. this means that the activity on the left port in no way slows the access time of the right port. both ports are identical in function to standard cmos static ram and can be accessed at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous read/write of, a non-semaphore location. semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non- semaphore portion of the dual-port sram. these devices have an automatic power-down feature controlled by ce , the dual-port sram enable, and sem, the semaphore enable. the ce and sem pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. this is the condition which is shown in truth table i where ce and sem are both high. systems which can best use the IDT70V35/34 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. these systems can benefit from a performance increase offered by the IDT70V35/34's hardware semaphores, which provide a lockout mechanism without requiring complex programming. software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. the IDT70V35/34 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. an advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. this can prove to be a major advantage in very high-speed systems. :? $.$- the semaphore logic is a set of eight latches which are indepen- dent of the dual-port sram. these latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphores provide a hardware assist for a use assignment method called ? token passing allocation. ? in this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. if the left processor wants to use this resource, it requests the token by setting the latch. this processor then verifies its success in setting the latch by reading it. if it was successful, it proceeds to assume control over the shared resource. if it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. the left processor can then either repeatedly request that semaphore ? s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. once the right side has relinquished the token, the left side should succeed in gaining control. the semaphore flags are active low. a token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. the eight semaphore flags reside within the IDT70V35/34 in a separate memory space from the dual-port sram. this address space is accessed by placing a low input on the sem pin (which acts as a chip select for the semaphore flags) and using the other control pins (address, oe , and r/ w ) as they would be used in accessing a standard static ram. each of the flags has a unique address which can be accessed by either side through address pins a 0 ? a 2 . when accessing the semaphores, none of the other address pins has any effect. when writing to a semaphore, only data pin d 0 is used. if a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see truth table v). that semaphore can now only be modified by the side showing the zero. when a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. the fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (a thorough discussion on the use of this feature follows shortly.) a zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. when a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. the read value is latched into one side ? s output register when that side's semaphore select ( sem ) and output enable ( oe ) signals go active. this serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. because of this latch, a repeated read of a semaphore in a test loop must cause either signal ( sem or oe ) to go inactive or the output will never change. a sequence write/read must be used by the semaphore in order to guarantee that no system level contention will occur. a processor requests access to shared resources by attempting to write a zero into a semaphore location. if the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see truth table v). as an example, assume a processor writes a zero to the left port at a free semaphore location. on a subsequent read, the processor will verify that it has written success- fully to that location and will assume control over the resource in question. meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. had a sequence of read/write been used instead, system contention problems could have occurred during the gap between the read and write cycles. it is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. the reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in figure 4. two sema- phore request latches feed into a semaphore flag. whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. this condition will continue until a one is written to the same semaphore request latch. should the other side ? s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side ? s request latch. the second side ? s flag will now stay low until its semaphore request latch is written to a one. from this it is easy to understand that, if a semaphore is 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 16 requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. the critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. the semaphore logic is specially designed to resolve this problem. if simultaneous requests are made, the logic guarantees that only one side receives the token. if one side is earlier than the other in making the request, the first side to make the request will receive the token. if both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. one caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. as with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. since any sema- phore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. .$b.<1 perhaps the simplest application of semaphores is their applica- tion as resource markers for the IDT70V35/34 ? s dual-port sram. say the 8k x 18 sram was to be divided into two 4k x 18 blocks which were to be dedicated at any one time to servicing either the left or right port. semaphore 0 could be used to indicate the side which would control the lower section of memory, and semaphore 1 could be defined as the indicator for the upper section of memory. to take a resource, in this example the lower 4k of dual-port sram, the processor on the left port could write and then read a zero in to semaphore 0. if this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 4k. meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into semaphore 0. at this point, the software could choose to try and gain control of the second 4k section by writing, then reading a zero into semaphore 1. if it succeeded in gaining control, it would lock out the left side. once the left side was finished with its task, it would write a one to semaphore 0 and may then try to gain access to semaphore 1. if semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into semaphore 1. if the right processor performs a similar task with semaphore 0, this protocol would allow the two processors to swap 4k blocks of dual-port sram with each other. the blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. all eight semaphores could be used to divide the dual-port sram or other shared resources into eight parts. sema- phores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. semaphores are a useful form of arbitration in systems like disk interfaces where the cpu must be locked out of a section of memory during a transfer and the i/o device cannot tolerate any wait states. with the use of semaphores, once the two devices has determined which memory area was ? off-limits ? to the cpu, both the cpu and the i/o devices could access their assigned portions of memory continu- ously without any wait states. semaphores are also useful in applications where no memory ? wait ? state is available on one or both sides. once a semaphore handshake has been performed, both processors can access their assigned ram segments at full speed. another application is in the area of complex data structures. in this case, block arbitration is very important. for this application one processor may be responsible for building and updating a data structure. the other processor then reads and interprets that data structure. if the interpreting processor reads an incomplete data structure, a major error condition may exist. therefore, some sort of arbitration must be used between the two different processors. the building processor arbitrates for the block, locks it and then is able to go in and update the data structure. when the update is completed, the data structure block is released. this allows the interpreting processor to come back and read the complete data structure, thereby guaran- teeing a consistent data structure. d 5624 drw 17 0 d q write d 0 d q write semaphore request flip flop semaphore request flip flop lport rport semaphore read semaphore read , figure 4. IDT70V35/34 semaphore logic 6.42 IDT70V35/34s/l preliminary high-speed 8/4k x 18 dual-port static ram industrial and commercial temperature r anges 17 2+ & " 5624 drw 18 a power 999 speed a package a process/ temperature range blank i (1) commercial (0 cto+70 c) industrial (-40 cto+85 c) pf 100-pin tqfp (pn100-1) 15 20 25 s l standard power low power xxxxx device type 144k (8k x 18-bit) 3.3v dual-port ram 72k (4k x 18-bit) 3.3v dual-port ram 70v35 70v34 idt speed in nanoseconds commercial only commercial & industrial commercial only , corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 831-754-4613 santa clara, ca 95054 fax: 408-492-8674 dualporthelp@idt.com www.idt.com the idt logo is a registered trademark of integrated device technology, inc. $ : 3 6/8/00: initial public offering 8/9/01: page 1 corrected i/o numbering page 5-7, 10 & 12 removed industrial temperature range offering for 25ns from dc & ac electrical characteristics page 17 removed industrial temperature range offering for 25ns speed from the ordering information added industrial temperature offering footnote 7/2/02: page 2 added date revision for pin configuration added 70v34 to datasheet notes: 1. contact your local sales office for industrial temp range for other speeds, packages and powers. 3 $ ' "preliminary' datasheets contain descriptions for products that are in early release. |
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